1. Field of the Invention
The present invention relates to a half tone-type phase shift mask, a method for forming a pattern using such a phase shift mask, and a manufacturing method for an electronic device.
2. Description of the Background Art
In recent years, increase in the integration and miniaturization of semiconductor integrated circuits have been notable. At the same time, miniaturization of circuit patterns formed on semiconductor substrates (hereinafter, simply referred to as wafers) has rapidly progressed.
Photolithographic technology, in particular, is widely recognized as a basic technology for pattern formation. Accordingly, a variety of developments and improvements have so far been carried out concerning photolithographic technology. However, miniaturization of patterns is continuing and demand for increase in pattern resolution is still growing.
Such photolithographic technology is a technology for transcribing a pattern on a photomask (original drawing) to a photoresist applied to a wafer and for patterning a lower layer film, which is subsequently etched, using the photoresist to which the pattern has been transcribed.
A development process is carried out on the photoresist at the time of the above described transcription of the photoresist, and a photoresist wherein the portion exposed to light is removed as a result of this development process is a positive type and a photoresist wherein the portion that has not been exposed to light is removed as a result of this development process is a negative type.
In general, the resolution limit R (nm) in a photolithographic technology using a scaling down exposure method is represented as:R=k1•λ/(NA)
Here, the wavelength (nm) of utilized light is denoted as λ, the numerical aperture of the projection optical system of the lenses is denoted as NA and a constant that depends on the condition for image formation and on the resist process is denoted as k1.
As can be seen from the above formula, a method for reducing the values of k1 and λ and for increasing the value of NA can be considered as a means for achieving an increase in the resolution limit R, that is to say, for gaining a microscopic pattern. That is to say, the constant that depends on the resist process is reduced and the wavelength may be continuously shortened and NA may be continuously increased.
From among the above, the reduction of the wavelength of the light source presents particularly difficult technical challenges and it becomes necessary to increase NA while using the same wavelength. In the case where NA is continuously increased; however, the depth of focus δ (δ=k2•λ/(NA)2) becomes shallow and a problem arises wherein the precision of the form and dimensions of the formed pattern deteriorate.
Therefore, research has been carried out to achieve the miniaturization of patterns by improving the photomask instead of the light source or the lenses. Recently, phase shift masks have attracted attention as photomasks that increase the degree of resolution of patterns.
A phase shift mask wherein effective dark portions are formed by combining the optimal dimensions of a translucent phase shift part and a transmission part in the configuration is disclosed as an example of the above described phase shift mask in Japanese Patent Laying-Open No. 10-293392.
In the case where a hole pattern is formed using a conventional phase shift mask, however, microscopic change in the dimensions of the mask is reflected as a great change in the dimensions of the resist pattern that is formed on the wafer, particularly when a pattern is formed having dimensions smaller than the wavelength of the exposure light. Therefore, a problem arises wherein the formation of a hole pattern having the desired dimensions becomes difficult. That is to say, there is a problem wherein advanced technology is required for the manufacture of a mask where mask costs become high because a mask pattern having a very small dimension error is required.
In addition, there is a problem with a pattern formed according to a conventional hole pattern formation method wherein the manufacturing yield of semiconductor integrated circuits is lowered due to lack of uniformity of dimensions or wherein the degree of integration is lowered when the intervals of pattern alignment are increased in order to avoid such lowering of the manufacturing yield.
In addition, there is a problem wherein a high precision mask, which is costly, becomes necessary in order to overcome the lack of uniformity in the pattern dimensions.